Temperature Estimation of HBM2 Channels with Tail Distribution of Retention Errors in FPGA-HBM2 Platform

High-bandwidth memory 2 (HBM2) vertically stacks multiple dynamic random-access (DRAM) dies to achieve a small form factor and high capacity. However, it is difficult diagnose HBM2 issues owing their structural complexity 2.5D integration with heterogeneous chips. The effects of the temperature at base logic die (TL), refresh interval stacked DRAM dies, were experimentally investigated by counting retention errors in eight channels an HBM2. TL was indirectly controlled heatsink (TS). lognormal distribution represents cell counts varying times. All Z-magnitudes (multiples standard deviation) over various cycle times (RCTs) up 2.045 s single channel 70 °C appeared below 4.4, which means that error bits belong tail distribution. Z-differences distinctively larger than same constant temperature, demonstrating difference resulted Z-differences. largest Z-difference 0.091 for all RCT 1.406 s, approximately 4.82 smaller between temperatures 80 channel. 72 as s.